The information here came from my own experiments and from file
"vgaregs.txt" in Finn Thoegersen's vgadoc4b.zip collection. See
the file "readme.1st" for information on this excellent reference.

I have removed the EGA-specific information and information on
features that I have not used. Registers that show an absolute
'1' or '0' in the bits reflect this, as do entire registers
shown as "don't care" (a dash shown for every bit). I have also
tried to put the information into a format that is easier on
the eyes (for me, anyway).
=====================================================================
CRTC CONTROLLER
=====================================================================
Write index	3D4h
Read index	3D4h
Write data	3D5h
Read data	3D5h
     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
CRTC|  b7   |  b6   |  b5   |  b4   |  b3   |  b2   |  b1   |  b0   |
00h |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

Horizontal total. This register should contain Htot - 5.


     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
CRTC|  b7   |  b6   |  b5   |  b4   |  b3   |  b2   |  b1   |  b0   |
01h |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

Horizontal displayed. This register should contain Hdisp - 1.


     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
CRTC|  b7   |  b6   |  b5   |  b4   |  b3   |  b2   |  b1   |  b0   |
02h |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

Character count at which horizontal blanking begins. My code sets
this to Hdisp. I don't know if this is correct - xxx


     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
CRTC|   1   |   0   |   0   |  b4   |  b3   |  b2   |  b1   |  b0   |
03h |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

Character count at which horizontal blanking ends. b5 is in CRTC
05h. My code sets this to 34 (Htot=100, Hdisp=80). b7 is one of the
pesky lock bits ("Access to Vertical Retrace registers if set"
	-- vgaregs.txt).


     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
CRTC|  b7   |  b6   |  b5   |  b4   |  b3   |  b2   |  b1   |  b0   |
04h |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

Character count at which horizontal retrace (sync) starts.


     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
CRTC|  b7   |   0   |   0   |  b4   |  b3   |  b2   |  b1   |  b0   |
05h |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

Character count at which horizontal retrace ends. b7 is b5 of the
horizontal blanking end value.


     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
CRTC|  b7   |  b6   |  b5   |  b4   |  b3   |  b2   |  b1   |  b0   |
06h |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

Vertical Total. This is actually Vtot - 2.
b9 and b8 are in the overflow register (CRTC 07h).


     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
CRTC|  b7   |  b6   |  b5   |  b4   |  b3   |  b2   |  b1   |  b0   |
07h |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

Overflow register; the 9th and 10th bits of various
vertical-related values.
	b7      b9 of Vertical Retrace Start (see CRTC 10h)
	b6      b9 of Vertical Display End   (see CRTC 12h)
	b5      b9 of Vertical Total         (see CRTC 06h)
	b4      b8 of Vertical Line Compare  (see CRTC 18h)
	b3      b8 of Vertical Blanking Start(see CRTC 15h)
	b2      b8 of Vertical Retrace Start (see CRTC 10h)
	b1      b8 of Vertical Display End   (see CRTC 12h)
	b0      b8 of Vertical Total         (see CRTC 06h)

     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
CRTC|   0   |   0   |   0   |  b4   |  b3   |  b2   |  b1   |  b0   |
08h |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

Smooth vertical scrolling. Useful only in text mode, since graphics
modes don't usually have a row structure (can do smooth vertical
scrolling simply by changing the display start address).


     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
CRTC|  ds   |  lc9  |  vb9  |  b4   |  b3   |  b2   |  b1   |  b0   |
09h |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

ds      Doublescan; doubles each scan line if set. This can also
	be accomplished by setting the character cell height to 2
        (xxx - I think...)
vb9     b9 of Vertical Blanking Start (see CRTC 15h)
lc9     b9 of Vertical Line Compare (see CRTC 18h)
bN	Character cell height - 1. For 25-row text modes, the font
	is 16 pixels high, and this value is 0Fh. In graphics
        modes, the value must be a power of two (xxx - I think...)


     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
CRTC|   0   |   0   | !csr  |  b4   |  b3   |  b2   |  b1   |  b0   |
0Ah |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

!csr    Turns off cursor if set.
bN      First scanline of cursor within character cell. For
        25-row text modes, the font is 16 pixels high, and
        this value is typically 0Dh (for underline cursor).


     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
CRTC|   0   |   0   |   0   |  b4   |  b3   |  b2   |  b1   |  b0   |
0Bh |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

Last scanline of cursor within character cell. For 25-row text
modes, the font is 16 pixels high, and this value is typically
0Eh (for underline cursor).


     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
CRTC|  b15  |  b14  |  b13  |  b12  |  b11  |  b10  |  b9   |  b8   |
0Ch |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|
     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
CRTC|  b7   |  b6   |  b5   |  b4   |  b3   |  b2   |  b1   |  b0   |
0Dh |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

These registers contain the start address of the display buffer,
offset from A0000h, B8000h, etc. See also register GC 06h.


     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
CRTC|  b15  |  b14  |  b13  |  b12  |  b11  |  b10  |  b9   |  b8   |
0Eh |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|
     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
CRTC|  b7   |  b6   |  b5   |  b4   |  b3   |  b2   |  b1   |  b0   |
0Fh |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

These registers contain the address of the cursor, offset from
A0000h, B8000h, etc. See also register GC 06h. The VGA cursor
works only in text modes.


     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
CRTC|  b7   |  b6   |  b5   |  b4   |  b3   |  b2   |  b1   |  b0   |
10h |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

Line count at which vertical retrace starts. b9 and b8 are in the
overflow register (CRTC 07h).


     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
CRTC|   0   |   0   |   1   |   1   |  b3   |  b2   |  b1   |  b0   |
11h |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

Line count at which vertical retrace ends. b7 is the other
annoying lock bit. It write-protects CRTC registers 0-7 when set.


     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
CRTC|  b7   |  b6   |  b5   |  b4   |  b3   |  b2   |  b1   |  b0   |
12h |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

Line count at which vertical display ends. b9 and b8 are in the
overflow register (CRTC 07h).


     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
CRTC|  b7   |  b6   |  b5   |  b4   |  b3   |  b2   |  b1   |  b0   |
13h |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

Offset. "Number of bytes in a scanline / K. Where K is 2 for byte
mode, 4 for word mode and 8 for Double Word mode." Setting this
register higher than Hdisp creates a "virtual" display, but the
display software must support it.


     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
CRTC|   0   | dwcm  |   0   |  b4   |  b3   |  b2   |  b1   |  b0   |
14h |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

dwcm    Doubleword clocking mode if set.
bN	Underline scanline within character cell.

     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
CRTC|  b7   |  b6   |  b5   |  b4   |  b3   |  b2   |  b1   |  b0   |
15h |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

Line count at which vertical blanking starts. b8 is in the
overflow register (CRTC 07h). b9 is in CRTC 09h. My code sets
this to VDisp + 8 (xxx - correct?)



     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
CRTC|   0   |  b6   |  b5   |  b4   |  b3   |  b2   |  b1   |  b0   |
16h |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

Line count at which vertical blanking ends.
My code sets this to VTot - 8 (xxx - correct?)


     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
CRTC|   1   | !wcm  |   1   |   0   |   0   |   0   |   1   |   1   |
17h |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

!wcm    Word clocking mode if clear.


     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
CRTC|  b7   |  b6   |  b5   |  b4   |  b3   |  b2   |  b1   |  b0   |
18h |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

Vertical line compare register. b8 is in the overflow register
(CRTC 07h). b9 is in CRTC 09h. Line compare is used for split-
screen effects. My code disables split screen by setting this
value to 3FFh.

=====================================================================
ATTRIBUTE CONTROLLER
=====================================================================
Write index	3C0h
Read index	3C0h
Write data	3C0h
Read data	3C1h

"Port 3C0h is special in that it is both address and data-write
 register. Data reads happen from port 3C1h. An internal flip-flop
 remembers whether it is currently acting as address or data
 register. Accesses to the attribute controller must be seperated
 by at least 250ns. Reading port 3dAh will reset the flip-flop to
 address mode.
	...
 If [b5 of port 0x3C0 is] set screen output is enabled and the
 palette can not be modified, if clear screen output is disabled
 and the palette can be modified."
     _______________________________________________________________
AC  |       |       |       |       |       |       |       |       |
0-  |   -   |   -   |  b5   |  b4   |  b3   |  b2   |  b1   |  b0   |
0Fh |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

Palette for 16-color text and graphics modes. Each of the 16
entries is an index into the 256-color DAC palette. b7 and b6 come
from attribute register 14h. Note, again, that this palette can not
be modified unless the display is shut off using b5 in the
attribute index register.


     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
AC  |   0   |  b6   |   0   |   -   | b/!i  | n/!e  |   0   | g/!t  |
10h |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

b6      "If set pixels are 8 bits wide. Used in 256 color modes."
b/!i	If set, text-mode attribute bit 7 is Blink, else Intense.
n/!e    If set, characters are (n)ine bits wide, else (e)ight bits.
	The ninth bit is the same as the background color, except
	for the line-drawing characters C0h - DFh.
g/!t    Graphics mode if set, else text.


     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
AC  |   -   |   -   |  b5   |  b4   |  b3   |  b2   |  b1   |  b0   |
11h |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

Overscan (border) color (index into the 256-color DAC palette).
b7 and b6 come from attribute register 14h.


     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
AC  |   -   |   -   |   -   |   -   |  P8   |  P4   |  P2   |  P1   |
12h |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

Color plane enable register. Since this register has four bits, it
appears to control writing to the planes. (You can write to all four
planes simultaneously, but read from only one at a time, so registers
controlling reading from the planes have only two bits -- see, for
example, GC 04h.)

This should probably be set to 0Fh in graphics modes and 03h in
text modes.


     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
AC  |   -   |   -   |   -   |   -   |  b3   |  b2   |  b1   |  b0   |
13h |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

Smooth horizontal scrolling. b3-b0 indicate the number of pixels
to shift the display left:
		9-bit		256-		other
	value   text mode	color mode	modes
	0	1		0		0
	1	2		n/a xxx - ?	1
	2	3		1		2
	3	4		n/a		3
	4	5		2		4
	5	6		n/a		5
	6	7		3		6
	7	8		n/a		7
	8	0		n/a		n/a
     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
AC  |   -   |   -   |   -   |   -   |  b3   |  b2   |   -   |   -   |
14h |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

b3,b2	b7 and b6 of the 6-bit palette and overscan colors.

=====================================================================
GRAPHICS CONTROLLER
=====================================================================
Write index	3CEh
Read index	3CEh
Write data	3CFh
Read data	3CFh
     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
GC  |   -   |   -   |   -   |   -   |  P8   |  P4   |  P2   |  P1   |
00h |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

Set/Reset data bits for each plane. Set/Reset works only in
Write Mode 0.


     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
GC  |   -   |   -   |   -   |   -   |  P8   |  P4   |  P2   |  P1   |
01h |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

Enables Set/Reset mode for each plane.


     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
GC  |   -   |   -   |   -   |   -   |   -   |   -   |   -   |   -   |
02h |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|
     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
GC  |   -   |   -   |  op1  |  op0  | rot3  | rot2  | rot1  | rot0  |
03h |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

opN     ALU operation to perform in Write Mode 2:
		value	operation
		0	(none)
		1	AND
		2	OR
		3	XOR
rotN	Number of bit positions to rotate data right before it
	is written to display memory.


     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
GC  |   -   |   -   |   -   |   -   |   -   |   -   |  p1   |  p0   |
04h |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

pN	Number of the plane accessed by video memory reads.


     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
GC  |   -   |  b6   |   0   |  eo   |   0   |   -   | wm1   | wm0   |
05h |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

b6      256-color graphics mode if set.
eo      Enables Even/Odd addressing mode when set.
wmN	Write Mode. These descriptions are lifted verbatim from
	vgaregs.txt:
	   0: Mode 0 works as a Read-Modify-Write operation.
	      First a read access loads the data latches of the VGA with the
	      value in video memory at the addressed location. Then a write
	      access will provide the destination address and the CPU data
	      byte. The data written is modified by the function code in the
	      Data Rotate register (3CEh index 3) as a function of the CPU
	      data and the latches, then data is rotated as specified by the
	      same register.
	   1: Mode 1 is used for video to video transfers.
	      A read access will load the data latches with the contents of
	      the addressed byte of video memory. A write access will write
	      the contents of the latches to the addressed byte. Thus a single
	      MOVSB instruction can copy all pixels in the source address byte
	      to the destination address.
	   2: Mode 2 writes a color to all pixels in the addressed byte of
	      video memory. Bit 0 of the CPU data is written to plane 0 et
	      cetera. Individual bits can be enabled or disabled through the
	      Bit Mask register (3CEh index 8).
	   3: Mode 3 can be used to fill an area with a color and pattern. The
	      CPU data is rotated according to 3CEh index 3 bits 0-2 and anded
	      with the Bit Mask Register (3CEh index 8). For each bit in the
	      result the corresponding pixel is set to the color in the
	      Set/Reset Register (3CEh index 0 bits 0-3) if the bit is set and
	      to the contents of the processor latch if the bit is clear.


     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
GC  |   -   |   -   |   -   |   -   | mem1  | mem0  |  eo   | g/!t  |
06h |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

memN	Sets base address of video memory:
		value	address range	mode
		0	A0000h-BFFF0h
		1	A0000h-AFFF0h	graphics
		2	B0000h-B7FF0h
		3	B8000h-BFFF0h	text
eo	Enables Even/Odd addressing mode.
g/!t    Graphics mode if set, else text. (xxx - This, according to
	vgaregs.txt. For my S3 video board and BIOS, this bit
	appears to always be 0)


     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
GC  |   -   |   -   |   -   |   -   |   -   |   -   |   -   |   -   |
07h |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|
     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
GC  |   b7  |   b6  |  b5   |  b4   |  b3   |  b2   |  b1   |  b0   |
08h |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

Bit mask used for Set/Reset mode (Write Mode 2).

=====================================================================
SEQUENCER
=====================================================================
Write index	3C4h
Read index	3C4h
Write data	3C5h
Read data	3C5h
     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
SEQ |   -   |   -   |   -   |   -   |   -   |   -   | !rst  |   1   |
00h |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

!rst    Puts sequencer in synchronous reset when clear. I get the
	impression that this should be done when the master dot
	clock is changed in the MISC register. It might also have
	to be done when any other sequencer register is changed.


     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
SEQ |   -   |   -   |   0   |   0   |  hdc  |   0   |   -   | e/!n  |
01h |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

hdc	Half Dot Clock. Divides dot clock by two when set.
e/!n    If set, characters are (e)ight bits wide, else (n)ine bits.
	This applies to graphics mode as well as text mode, since
	horizontal timings are given in terms of character clocks.


     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
SEQ |   -   |   -   |   -   |   -   |  P8   |  P4   |  P2   |  P1   |
02h |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

These bits enable writes to the corresponding plane. In text mode,
they chose between font data or text/attribute data. In 16-color
graphics modes, they chose the color of pixels written to video
memory.


     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
SEQ |   -   |   -   | hfb2  | hfa2  | hfb1  | hfb0  | hfa1  | hfa0  |
03h |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

hfbN	Selects VGA hardware font to be used when b3 of the
	text-mode attribute byte is 1.
hfaN	Selects VGA hardware font to be used when b3 of the
	text-mode attribute byte is 0.

	b3 of the attribute byte is also the Intense bit for the
	foreground color. For 512-character fonts, the palette
	must be reprogrammed to sacrifice the top 8 of 16
	foreground colors.

	The fonts occupy plane P4 at the following offsets:
		font	offset		font	offset
		0	 0		4	 8K
		1	16K		5	24K
		2	32K		6	40K
		3	48K		7	56K


     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
SEQ |   -   |   -   |   -   |   -   |  ch4  |  !eo  |   1   | g/!t  |
04h |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

ch4     Enables Chain4 addressing mode. This uses address bits 0
	and 1 to select one of the four planes. BIOS mode 13h uses
	Chain4; unchained 256-color modes are known collectively
	as Mode X.
!eo	Enables Even/Odd addressing mode when clear. This mode uses
	address bit 0 to select between planes P4/P1 (even
	addresses) and planes P8/P2 (odd addresses). BIOS text
	modes use Even/Odd addressing to make the text in plane P1
	and the attributes in plane P2 appear at alternating
	addresses.
g/!t    Graphics mode if set, else text mode.

=====================================================================
MISCELLANEOUS REGISTER
=====================================================================
Write index	(none)
Read index	(none)
Write data	3C2h
Read data	3CCh
     _______________________________________________________________
    |       |       |       |       |       |       |       |       |
MISC|  nvs  |  nhs  |  bs   |   -   |   0   |  dcs  |   1   |   1   |
    |       |       |       |       |       |       |       |       |
    |_______|_______|_______|_______|_______|_______|_______|_______|

nvs	Negative Vertical Sync if set.
nhs	Negative Horizontal Sync if set. Old fixed-frequency (xxx - ?)
	monitors rely on sync pulse polarity to set vertical
	resolution:
		nvs	nhs	lines
		0	0	(reserved)
		0	1	400
		1	0	350
		1	1	480
bs	Selects high 64K bank (even/odd addressing mode only).
dcs	Dot Clock Select: 28.35 MHz if set, 25.20 MHz if clear.
	The dot clock may also be divided by 2 (see sequencer
	register 01h).

=====================================================================
DAC
=====================================================================
Write index	3C8h
Read index	3C7h
Write data	3C9h
Read data	3C9h

To write the 256-color palette:
	- write first color index to I/O address 3C8h
	- while more_colors_to_write:
		- write 6-bit red value to I/O address 3C9h
		- write 6-bit green value to I/O address 3C9h
		- write 6-bit blue value to I/O address 3C9h
The color index at 3C8h will be automatically incremented
after the third write (the blue value) to 3C9h.

To read the 256-color palette:
	- write first color index to I/O address 3C7h
	- while more_colors_to_read:
		- read 6-bit red value from I/O address 3C9h
		- read 6-bit green value from I/O address 3C9h
		- read 6-bit blue value from I/O address 3C9h
The color index at 3C7h will be automatically incremented
after the third read (the blue value) from 3C9h.

