FIFO Control Register (FCR), bit b3 enables DMA

TXRDY, RXRDY, Pins 24, 29: Transmitter and Receiver
DMA signalling is available through two pins (24 and 29).
When operating in the FIFO mode, one of two types of DMA
signalling per pin can be selected via FCR3. When operat-
ing as in the 16450 Mode, only DMA mode 0 is allowed.
Mode 0 supports single transfer DMA where a transfer is
made between CPU bus cycles. Mode 1 supports multi-
transfer DMA where multiple transfers are made continu-
ously until the RCVR FIFO has been emptied or the XMIT
FIFO has been filled.

RXRDY, Mode 0: When in the 16450 Mode (FCR0=0) or in
the FIFO Mode (FCR0=1, FCR3=0) and there is at least 1
character in the RCVR FIFO or RCVR holding register, the
RXRDY pin (29) will be low active. Once it is activated the
RXRDY pin will go inactive when there are no more charac-
ters in the FIFO or holding register.

RXRDY, Mode 1: In the FIFO Mode (FCR0=1) when the
FCR3=1 and the trigger level or the timeout has been
reached, the RXRDY pin will go low active. Once it is acti-
vated it will go inactive when there are no more characters
in the FIFO or holding register.

TXRDY, Mode 0: In the 16450 Mode (FCR0=0) or in the
FIFO Mode (FCR0=1, FCR3=0) and there are no charac-
ters in the XMIT FIFO or XMIT holding register, the TXRDY
pin (24) will be low active. Once it is activated the TXRDY
pin will go inactive after the first character is loaded into the
XMIT FIFO or holding register.

TXRDY, Mode 1: In the FIFO Mode (FCR0=1) when
FCR3=1 and there are no characters in the XMIT FIFO, the
TXRDY pin will go low active. This pin will become inactive
when the XMIT FIFO is completely full.
