Format of PCI Configuration Data:
Offset	Size	Description	(Table 00878)
 00h	WORD	vendor ID (read-only) (see #00732 at AX=B102h)
		FFFFh returned if requested device non-existent
 02h	WORD	device ID (read-only)
 04h	WORD	command register (see #00879)
 06h	WORD	status register (see #00880)
 08h	BYTE	revision ID
 09h  3 BYTEs	class code
		bits 7-0: programming interface
		bits 15-8: sub-class
		bits 23-16: class code (see also #F0085)
 0Ch	BYTE	cache line size
 0Dh	BYTE	latency timer
 0Eh	BYTE	header type
		bits 6-0: header format
			00h other
			01h PCI-to-PCI bridge
			02h PCI-to-CardBus bridge
		bit 7: multi-function device
 0Fh	BYTE	Built-In Self-Test result (see #00881)
---header type 00h---
 10h	DWORD	base address 0 (see #00882)
		(OpenHCI) base address of host controller registers (see #00902)
 14h	DWORD	base address 1
 18h	DWORD	base address 2
 1Ch	DWORD	base address 3

 20h	DWORD	base address 4
 24h	DWORD	base address 5
 28h	DWORD	CardBus CIS pointer (read-only) (see #00889)
 2Ch	WORD	subsystem vendor ID or 0000h
 2Eh	WORD	subsystem ID or 0000h
 30h	DWORD	expansion ROM base address (see #00883)
 34h	BYTE	offset of capabilities list within configuration space (R/O)
		(only valid if status register bit 4 set) (see #00884)
 35h  3 BYTEs	reserved
 38h	DWORD	reserved
 3Ch	BYTE	interrupt line
		00h = none, 01h = IRQ1 to 0Fh = IRQ15
 3Dh	BYTE	interrupt pin (read-only)
		(00h = none, else indicates INTA# to INTD#)
 3Eh	BYTE	minimum time bus master needs PCI bus ownership, in 250ns units
		(read-only)
 3Fh	BYTE	maximum latency, in 250ns units (bus masters only) (read-only)
 40h 48 DWORDs	varies by device (see #00919,#00920,#01055,#01083)

Format of PCI Configuration for Intel 82371FB/82371SB Function 1 (IDE):
Offset	Size	Description	(Table 01214)
 00h 64 BYTEs	header (see #00878)
                (vendor ID 8086h, device ID 1230h/7010h)
 20h	DWORD	Bus Master Interface Base Address
		(see PORT xxxxh"Intel 82371SB")
 40h	WORD	IDE timing modes, primary channel (see #01223)
 42h	WORD	IDE timing modes, secondary channel (see #01223)
 44h	BYTE	(82371SB) slave IDE timing register (see #01224)
 45h 187 BYTEs	reserved
SeeAlso: #01167,#01215,PORT xxxxh"Intel 82371SB"

Bitfields for PCI Configuration Command Register:
Bit(s)	Description	(Table 00879)
 0	I/O access enabled
 1	memory access enabled
 2	bus master enable
 3	special cycle recognition enabled
 4	memory write and invalidate enabled
 5	VGA palette snoop enabled
 6	parity error response enabled
 7	wait cycles enabled
 8	system error (SERR# line) enabled
 9	fast back-to-back transactions enabled
 15-10	reserved
SeeAlso: #00878,#00880

Format of PCI Configuration Status Register:
Bit(s)	Description	(Table 00880)
 3-0	reserved (0)
 4	new capabilities list is present (first entry pointed at by byte at
	  34h or 14h)
 5	capable of running at 66 MHz
 6	UDF supported
 7	capable of fast back-to-back transactions
 8	data parity error reported
 10-9	device select timing
	00 fast
	01 medium
	10 slow
	11 reserved
 11	signaled target abort
 12	received target abort
 13	received master abort
 14	signaled system error (device is asserting SERR# line)
 15	detected parity error (set even if parity error reporting is disabled)
Note:	bits 12, 13 and 15 are cleared by writing a 1 into the corresponding
	  bit
SeeAlso: #00878,#00879

Bitfields for PCI Configuration Built-In Self-Test register:
Bit(s)	Description	(Table 00881)
 3-0	completion code (0000 = successful)
 5-4	reserved
 6	start BIST (set to one to start, cleared automatically on completion)
 7	BIST-capable
Notes:	this register is hardwired to 00h if no BIST capability
	software should timeout the BIST after two seconds
SeeAlso: #00878

Bitfields for PCI Configuration Base Address:
Bit(s)	Description	(Table 00882)
 0	address type (0 = memory space, 1 = I/O space)
---memory address---
 2-1	address type
	00 anywhere in first 4GB
	01 below 1MB
	10 anywhere in 64-bit address space
	11 reserved
 3	prefetchable
 31-4	bits 31-4 of base memory address if addressable in first 1MB or 4GB
 63-4	bits 63-4 of base memory address if addressable in 64-bit memory
	(bits 63-32 are stored in the following base address DWORD)
---I/O address---
 1	reserved
 31-2	bits 31-2 of base I/O port
SeeAlso: #00878,#00902

Bitfields for PCI Configuration Expansion ROM Address:
Bit(s)	Description	(Table 00883)
 0	address decode enable (ROM address is valid)
 10-1	reserved
 31-11	bits 31-11 of ROM's starting physical address
SeeAlso: #00878

Format of PCI Capabilities List:
Offset	Size	Description	(Table 00884)
 00h	BYTE	capability identifier
		01h PCI Power Managment
 01h	BYTE	offset of next item (within configuration space) or 00h
      N	BYTEs	varies by capability type
---PCI Power Management---
 02h	WORD	power managment capabilities (see #00885) (read-only)
 04h	WORD	power managment capabilities status register (see #00886)
 06h	BYTE	PMCSR bridge support extensions (see #00887)
 07h	BYTE	(optional) read-only data register (see #00888)
Note:	this information is from the v0.93 draft of the specification and is
	  subject to change
SeeAlso: #00878,#00880

Bitfields for PCI Power Management Capabilities:
Bit(s)	Description	(Table 00885)
 15	reserved (0)
 14-12	PME# support
	bit 12: PME# can be asserted from power state D0
	bit 13: PME# can be asserted from power state D1
	bit 14: PME# can be asserted from power state D2
 11	reserved (0)
 10	D2 power state supported
 9	D1 power state supported
 8	full-speed clock is required in state D0 for proper operation
	(if clear, device may be run at reduced clock except when actually
	  being accessed)
 7-6	dynamic clock control support
	00 not bridge, no dynamic clock control, or secondary bus' clock is
	      is tied to primary bus' clock
	01 bridge is capable of dynamic clock control
	10 reserved
	11 secondary bus has independent clock, but dynamic clock not supported
 5	device-specific initialization is required
 4	auxiliary power required for PME# generation
 3	PCI clock required for PME# generation
 2-0	specification version
	001 = v1.0; four bytes of power management registers
Note:	this information is from the v0.93 draft of the specification and is
	  subject to change
SeeAlso: #00884,#00886,#00887

Bitfields for PCI Power Management Capabilities Status Register:
Bit(s)	Description	(Table 00886)
 15	PME status: if set, PME# is (or would be) asserted
	writing a 1 to this bit clears it
 14-13	(read-only) scale factor to apply to contents of Data register
	00 unknown (or unimplemented data)
	01 x0.1
	10 x0.01
	11 x0.001
 12-9	(read-write) data select (see #00888)
 8	(read-write) enable PME# assertion
 7-5	reserved (0)
 4	(read-write) enable dynamic data reporting
	when set, PME# is asserted whenever the value in the Data register
	  changes significantly
 3-2	reserved (0)
 1-0	(read-write) current power state
	00 = D0
	...
	11 = D3
Note:	this information is from the v0.93 draft of the specification and is
	  subject to change
SeeAlso: #00884,#00885,#00887

Bitfields for PCI Power Management PMCSR bridge support extension:
Bit(s)	Description	(Table 00887)
 7	(read-only) Bus Power Control Enable
 6	(read-only) Bus Power State B3 supported
 5	(read-only) Bus Power State B2 supported
 4	dynamic clock control enable
 3-0	reserved (0)
Note:	this information is from the v0.93 draft of the specification and is
	  subject to change
SeeAlso: #00884,#00885,#00886

(Table 00888)
Values for PCI Power Management Data Select:
 00h	D0-state power consumed in watts (+20%/-10%)
 01h	D1-state power consumed in watts (+20%/-10%)
 02h	D2-state power consumed in watts (+20%/-10%)
 03h	D3-state power consumed in watts (+20%/-10%)
 04h	D0-state power dissipated into chassis in watts
 05h	D1-state power dissipated into chassis in watts
 06h	D2-state power dissipated into chassis in watts
 07h	D3-state power dissipated into chassis in watts
 08h-0Fh reserved
SeeAlso: #00886

Bitfields for Intel 82371FB/82371SB/82371MX IDE timing modes:
Bit(s)	Description	(Table 01223)
 15	IDE decode enable
 14	(82371SB) slave IDE timing register enable (see #01224)
	(82371MX) primary/secondary address decode (=0 primary, =1 secondary)
 13-12	IORDY# sample point
	00 five clocks after DIOx# assertion
	01 four clocks
	10 three clocks
	11 two clocks
 11-10	reserved
 9-8	recovery time between IORDY# sample point and DIOx#
	00 four clocks
	01 three clocks
	10 two clocks
	11 one clock
 7	(FB/SB) DMA timing enable only, drive 1
	(MX) reserved
 6	prefetch and posting enable, drive 1
 5	IORDY# sample point enable drive select 1
 4	fast timing bank drive select 1
 3	(FB/SB) DMA timing enable only, drive 0
	(MX) reserved
 2	prefetch and posting enable, drive 0
 1	IORDY# sample point enable drive select 0
 0	fast timing bank drive select 0
SeeAlso: #01214,#01168

Bitfields for Intel 82371SB slave IDE timing register:
Bit(s)	Description	(Table 01224)
 7-6	secondary drive 1 IORDY# sample point
	00 five clocks after DIOx# assertion
	01 four clocks
	10 three clocks
	11 two clocks
 5-4	secondary drive 1 recovery time
	00 four clocks
	01 three clocks
	10 two clocks
	11 one clock
 3-2	primary drive 1 IORDY# sample point
 1-0	primary drive 1 recovery time
SeeAlso: #01223

PORT xxxx - Intel 82371, OPTi "Vendetta" (82C750) - Bus Master IDE Registers

+000  RW  command register, primary channel (see #P1092)
+002  Rw  status register, primary channel (see #P1093)
+004d RW  IDE descriptor table pointer, primary channel (see #P1094)
+008  RW  command register, secondary channel (see #P1092)
+00A  Rw  status register, secondary channel (see #P1093)
+00Cd RW  IDE descriptor table pointer, secondary channel (see #P1094)

Bitfields for Intel 82371 Bus Master IDE command register:
Bit(s)	Description	(Table P1092)
 7-4	reserved
 3	bus master read/write control
	=0 read
	=1 write
 2-1	reserved
 0	start/stop bus master
	=1 start
	=0 stop
SeeAlso: #P1093,#P1094

Bitfields for Bus Master IDE status register:
Bit(s)	Description	(Table P1093)
 7	(Intel) reserved (0)
	(OPTI "Vendetta") both channels operable at same time (read-only)
 6	drive 1 is DMA-capable
 5	drive 0 is DMA_capable
 4-3	reserved
 2	IDE interrupt pending
	write 1 to this bit to clear it
 1	IDE DMA error
	write 1 to this bit to clear it
 0	bus master IDE active (read-only)
SeeAlso: #P1092,#P1094

Bitfields for Bus Master IDE descriptor table pointer register:
Bit(s)	Description	(Table P1094)
 31-2	descriptor table base address bits 31-2
 1-0	reserved (0)
Notes:	(Intel 82371) the descriptor table must not cross a 4K boundary
	(OPTi "Vendetta") the descriptor table must not cross a 64K boundary
SeeAlso: #P1092,#P1093
